1. Field of the Invention
This invention relates to integrated circuit chips and, in particular, to differential input buffers capable of reducing clock signal skew.
2. Description of the Related Art
Internal circuit functions in synchronous integrated circuits, e.g. SDRAM chips, are performed in response to transitions of an internal clock signal. Clock signals are signals that vary between a low voltage and a high voltage at regular intervals and are referenced to a fixed voltage, typically either the low voltage or the high voltage. The internal clock signal is derived from an external clock signal that has been passed through an input buffer as it enters the integrated circuit. The input buffer detects transitions in the external clock signal and outputs an internal clock signal, usually at a different reference voltage than the external clock signal.
Some circuits require differential input clock signals at a pair of terminals, i.e., signals that vary in opposed fashion. For example, delay stages in many delay-locked loops require high-speed, low-skew differential inputs for proper operation. Additionally, phase comparators in such delay-locked loops may also utilize differential input signals. Because integrated circuit devices that include such delay-locked loops often receive only single-ended signals, the single-ended signals often must be converted to differential signals. Thus, the input buffer circuit may also produce complimentary internal clock signals where one signal follows the external clock signal, and the second signal follows the inverse of the external clock signal.
However, when a buffer circuit produces complimentary output signals, the output signals are susceptible to skew. For example, a first data signal generated and driven using a first internal clock signal is to be sampled by a second data signal driven by a second internal clock signal, the inverse of the first internal clock signal. If the two clock signals are skewed, e.g. they are out of phase with one another, then the first data signal may arrive too early or too late to be sampled by the second data signal. This situation is referred to as a xe2x80x9crace conditionxe2x80x9d and is a result of excessive skew between two or more internal clock signals. Race conditions can cause an incorrect data value to be read when a data signal is sampled since the first data signal is not present when it is to be sampled. Therefore, race conditions can cause an integrated circuit to malfunction.
One approach to converting a single-ended signal into a differential signal is to run a single-ended external clock signal CLK through an inverter to produce an inverted signal CLK . The noninverted and inverted signals CLK, CLK  are then output at a pair of terminals as a differential signal. Because of the extra path length the inverted signal CLK  travels, this signal arrives at the pair of terminals slightly after the noninverted signal CLK. The skew of the two signals is typically on the order of 50 picoseconds or more, even with a very fast inverter. Such skew times are unacceptable for some applications, such as very low jitter delay locked loops and phase-locked loops. In such circuits, skewed input signals can cause instability, drift and jitter in the output signals.
The skew of signals CLK and CLK  is illustrated in the timing diagram shown in FIG. 8. Signal CLK is low and signal CLK  is high at time T1. At time T1, signal CLK transitions to a high state. Signal CLK  begins to transition to a low state at time T2, the same time signal CLK reaches the end of its transition to a high state. At time T3, CLK reaches the end of its transition to a low state. The difference between T2 and T3 represents the skew of the signals CLK and CLK .
In some cases the external clock signals arrive at an input buffer already in complimentary form. FIG. 9 illustrates in circuit diagram form a conventional differential input buffer circuit 200 used to produce and drive an internal clock signal CLK and inverse clock signal CLK  from external clock signals XCLK and XCLK , respectively. The circuit 200 generally comprises an input buffer 202 and a pair of clock driver circuits 204.
A typical input buffer 202 for use in a conventional differential input buffer circuit 200 is illustrated in circuit diagram form in FIG. 10. N-channel transistors 204 and 206 are connected to P-channel input transistors 208 and 210, respectively, to form a differential amplifier. The common source of P-channel input transistors 208 and 210 is connected to voltage supply Vcc 212 through P-channel transistors 214 and 216. The common drain of N-channel input transistors 204 and 206 is connected to ground VSS 218 through N-channel transistor 220. Clock signal CLK on line 222 is coupled to the gate of P-channel transistors 208 and 210 and N-channel transistors 204 and 206. N-channel transistors 226 and 228 are connected to P-channel transistors 230 and 232, respectively, to form a differential amplifier. The common source of P-channel transistors 230 and 232 is connected to positive voltage supply VCC 212 through P-channel transistors 214 and 216. The common drain of N-channel input transistors 226 and 228 is connected to ground VSS 218 through N-channel transistor 220. Clock signal CLK  on line 224 is coupled to the gate of P-channel transistors 230 and 232 and N-channel transistors 226 and 228.
The output of the differential amplifiers at terminals 234 and 236 is coupled to the input of a pair of high threshold inverters formed by, respectively, P-channel transistors 238, 242, N-channel transistors 240, 244, voltage supplies 246, 250, and ground points 248, 252. The output of the high threshold inverters at terminals 254 and 256 provides internal clock signals CLK and CLK .
In operation, when the enabling signal ENi is high, P-channel transistor 214 is off and N-channel transistors 258 and 260 are off due to the inversion of the signal ENi by inverter 262. When control signal ENi goes low, P-channel transistor 214 is on, N-channel transistors 258 and 260 are on, and the differential amplifier is enabled.
When XCLK is high, P-channel transistors 208 and 210 are off and N-channel transistors 204 and 206 arc on. Simultaneously, XCLK  is low since it is the inverse of XCLK and P-channel transistors 230 and 232 are on and N-channel transistors 226 and 228 arc off. Therefore, when XCLK is high and XCLK  is low, terminal 234 is driven low, to VSS, and terminal 236 is driven high, to VCC. When terminal 234 is low, P-channel transistor 238 is on and N-channel transistor 240 is off, driving terminal 246 high, to VCC. When terminal 236 is high, P-channel transistor 242 is off and N-channel transistor 244 is on, driving terminal 248 low, to VSS. In comparison, when XCLK is low and XCLK  is high, terminal 234 is high which drives terminal 246 low and terminal 236 is low which drives terminal 248 high.
While such a circuit buffers the external clock signals, it does not eliminate any pre-existing skew between the external clock signals. In addition, though it is useful for the regulated portion of an integrated circuit the resulting internal clock signals do not track well with the address and data inputs across the circuits operating voltage. Due to the large number and interdependence of transistors, the gate loading for this circuit leads to crossing point accuracy problems in response to fluctuations in voltage and temperature conditions.
Thus, there exists a need for a circuit to produce internal clock signals which exhibit less clock signal skew and which track well with address and data inputs, and are less susceptible to environmental conditions.
The present invention provides a clock signal input circuit that is able to provide inverse internal clock signals exhibiting reduced skew which are generated by the same input buffer as the address and data signals on an integrated circuit.
In a preferred embodiment, a skewed external noninverse clock signal and a corresponding external inverse clock signal are passed through respective reference voltage input buffers to produce internal clock signals. The internal clock signals are generated by the same input buffer as the address and data inputs. To reduce skew, back to back inverters are connected to both lines carrying the noninverted and inverted internal clock signals from the respective reference voltage input buffers. The slower internal clock signal has an extra inverter driving it when it switches states, e.g. from a high state to a low state, and the faster internal clock signal has an extra inverter fighting it when it switches states. The skew of the two signals is reduced, allowing for faster operation of the integrated circuit and a reduction in error in downstream circuits using the two signals.